Samsung and Cadence just announced the successful tapeout of a 20nm logic test chip that includes the ARM Cortex-M0 microprocessor core. This announcement is yet more evidence that Moore’s Law is alive and kicking…even below 28nm. This test chip design proves out key aspects of the 20nm design chain including the ARM IP, libraries, foundry enablement, and EDA software.

Meanwhile, it’s interesting to contemplate the ARM Cortex-M0 microprocessor core used for the test chip. The ARM Cortex-M0 is ARM’s smallest 32-bit processor core. It has a mere 56 instructions, largely drawn from the original ARM Thumb 16-bit instruction set. The ARM Cortex-M0 instruction set includes 35 instructions drawn from the Thumb instruction set first used in the ARM7TDMI processor core plus another 21 Thumb-2 instructions. The ARM Cortex-M0 processor core is upward compatible with the larger ARM Cortex-M3 processor core. Both share these 56 instructions and then the ARM Cortex-M3 processor core has another 99 instructions in its instruction set.

The restricted number of instructions gives the ARM Cortex-M0 its small physical footprint. In minimal configuration, the ARM Cortex-M0 processor consumes a mere 12,000 gates. That’s about one third of the size of the ARM7TDMI hard-core processor that was designed back in the 1990s. With its small physical size and small code footprint, the ARM Cortex-M0 processor is aimed squarely at the 8- and 16-bit embedded markets. Some variants of the venerable 8051 8-bit microcontroller core are actually larger than the ARM Cortex-M0 processor core, according to a 2009 Microprocessor Report article written by Tom Halfhill (“ARM’s Smallest Thumb,” March 2, 2009, subscription required).

According to this article, the ARM Cortex-M0 processor has a footprint of only 0.04 mm2 when fabricated with a generic 90nm IC process technology so you can imagine how small this processor is when implemented with a process technology that’s four or five generations newer. Even fully configured, an ARM Cortex-M0 microprocessor core requires only 24,000 gates. Still tiny at 20nm.

The same Microprocessor Report article amusingly calculates that 17,475 ARM Cortex-M0 processor cores implemented in a generic 90nm process technology would fit on an Intel “Tukwila” Itanium server processor, which measures just hair under 700 mm2. By my calculations, that means that approximately half a million ARM Cortex-M0 processor cores would fit on that same die (not including any on-chip memory or interconnect). We have no known way of programming such a massively parallel system at this point.

But, in fact, that’s not the point. We’re not trying to see how many processors we can get to dance on the head of a pin.

Halfhill’s article also discusses the low-power aspects of such a small processor core. The ARM Cortex-M0 is really designed for low-power applications. Even implemented in a 90nm generic process technology, the core consumes a mere 0.015 milliwatts/MHz. Properly implemented in a 20nm process technology, the power consumption could be much, much lower. Back at 90nm, Halfhill’s article discusses the possibility of a Zigbee node running for 30 years on a CR2032 battery (if self-discharge or chemical leakage doesn’t kill the battery first).

So what are the low-power aspects of Samsung’s 20nm process? Richard Goering interviewed Ana Hunter, vice president of foundry services at Samsung, and one of the questions he asked was about power and performance for the process technology. She replied “From 28nm to 20nm we’re seeing about a 35% performance improvement at the same leakage level. We’re seeing about a 50% leakage reduction at the same performance.”

That’s one of the exciting aspects to this announcement for me. What about you?

You can read about the announcement here. It names the numerous Cadence EDA tools used to create the 20nm test chip.

Update: You can read more details in the July 12 EETimes article on this topic: http://www.eetimes.com/electronics-news/4217768/Samsung-Foundry-ARM-test-chip